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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
PRELIMINARY
March 1999
NM25C640 64K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C640 is a 65,536-bit CMOS EEPROM with an SPI compatible serial interface. The NM25C640 is designed for data storage in applications requiring both non-volatile memory and insystem data updates. This EEPROM is well suited for applications using the 68HC11 series of microcontrollers that support the SPI interface for high speed communication with peripheral devices via a serial bus to reduce pin count. The NM25C640 is implemented in Fairchild Semiconductor's floating gate CMOS process that provides superior endurance and data retention. The serial data transmission of this device requires four signal lines to control the device operation: Chip Select (CS), Clock (SCK), Data In (SI), and Serial Data Out (SO). All programming cycles are completely self-timed and do not require an erase before WRITE. BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection. Additionally, separate WRITE enable and WRITE disable instructions are provided for data protection. Hardware data protection is provided by the WP pin to protect against inadvertent programming. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence.
Features
s 2.75 MHz clock rate @ 4.5V to 5.5V 2.1 MHz @ 2.7V to 4.5V s 65,536 bits organized as 8,192 x 8 s Multiple chips on the same 3-wire bus with separate chip select lines s Self-timed programming cycle s Simultaneous programming of 1 to 32 bytes at a time s Status register can be polled during programming to monitor READY/BUSY s Write Protect (WP) pin and write disable instruction for both hardware and software write protection s Block write protect feature to protect against accidental writes s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin DIP or 8-Pin SO
Block Diagram
CS HOLD SCK SI Instruction Register
Instruction Decoder Control Logic and Clock Generators
VCC VSS WP
Address Counter/ Register
Program Enable VPP EEPROM Array 65,536 Bits (8,192 x 8)
High Voltage Generator and Program Timer
Decoder 1 of 8,192
Read/Write Amps
Data In/Out Register 8 Bits
Data Out Buffer
SO
Non-Volatile Status Register
DS500041-1
(c) 1999 Fairchild Semiconductor Corporation NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N) and SO Package (M8) CS SO WP VSS 1 2 NM25C640 3 4 Top View 6 5 SCK SI
DS500041-2
8 7
VCC HOLD
Pin Names
CS SO WP VSS SI SCK HOLD VCC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply
Ordering Information NM 25 C XX LZ E XX
Package Temp. Range
Letter
N M8 None V E Blank L LZ 640 C Interface 25 NM
Description
8-Pin DIP 8-Pin SO 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V and <1A Standby Current 64K, mode 0 CMOS SPI Fairchild Nonvolatile Memory
Voltage Operating Range
Density/Mode
2
NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Standard Voltage 4.5 VCC 5.5V Specifications Operating Conditions Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating -65C to +150C +6.5V to -0.3V +300C 2000V Ambient Operating Temperature NM25C640 NM25C640E NM25C640V Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V VCC 5.5V (unless otherwise specified)
Symbol
ICC ICCSB IIL IOL VIL VIH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage CMOS Input Low Voltage CMOS Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min CS High Time CS Setup Time Data Setup Time HOLD Setup Time CS Hold Time Data Hold Time HOLD Hold Time Output Delay Output Hold Time HOLD to Output Low Z Output Disable Time HOLD to Output High Z Write Cycle Time
Conditions
CS = VIL CS = VCC VIN = 0 to VCC VOUT = GND to VCC
Min
Max
3 50
Units
mA A A A V V V V
-1 -1 -0.3 VCC * 0.7
+1 +1 VCC * 0.3 VCC + 0.3 0.4
IOL = 2.1 mA IOH = -0.8 mA VCC - 0.8
2.75 2.0 2.0 (Note 2) (Note 2) (Note 3) 155 155 240 176 50 90 155 50 90 CL = 200 pF 0 240 CL = 200 pF 290 240 1-32 Bytes 10 135
MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Capacitance TA = 25C, f = 2.1/1 MHz (Note 4)
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200 pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ Max Units
3 2 8 6 pF pF
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns. Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 4: This parameter is periodically sampled and not 100% tested.
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NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Low Voltage 2.7V VCC 4.5V Specifications Operating Conditions Absolute Maximum Ratings (Note 5)
Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating -65C to +150C +6.5V to -0.3V +300C 2000V Ambient Operating Temperature NM25C640L/LZ NM25C640LZ/LZE NM25C640LV Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 2.7V-4.5V
DC and AC Electrical Characteristics 2.7V VCC 4.5V (unless otherwise specified)
Symbol
ICC ICCSB IIL IOL VIL VIH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min. CS High Time CS Setup Time Data Setup Time HOLD Setup Time CS Hold Time Data Hold Time HOLD Hold Time Output Delay Output Hold Time HOLD Output Low Z Output Disable Time HOLD to Output Hi Z Write Cycle Time
Part
L LZ
Conditions
CS = VIL CS = VCC VIN = 0 to VCC VOUT = GND to VCC
25C640L/LE 25C640LZ/LZE Min. Max.
3 10 1 -1 -1 -0.3 0.7 * VCC 1 1 0.3 * VCC VCC + 0.3 0.4 VCC - 0.8 2.1 2.0 2.0
25C640LV Min Max
3 10 N/A -1 -1 -0.3 0.7 * VCC 1 1 0.3 * VCC VCC + 0.3 0.4 VCC - 0.8 1.0 2.0 2.0 410 410 500 500 100 240 500 100 240
Units
mA A A A A V V V V MHz s s ns ns ns ns ns ns ns ns ns
IOL = 1.6 mA IOH = -0.8 mA
(Note 6) (Note 6) (Note 7)
190 190 240 240 100 90 240 100 90
CL = 200 pF 0
240 0 100
500
ns ns
240 500 240 15
ns ns ns ms
CL = 200 pF
240 100
1-32 Bytes
15
Capacitance TA = 25C, f = 2.1/1 MHz (Note 8)
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ Max Units
3 2 8 6 pF pF
Note 5: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns. Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 8: This parameter is periodically sampled and not 100% tested.
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NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
AC Test Conditions (Continued)
VIH CS VIL VIH SCK VIL VIH SI VIL VOH SO VOL
FIGURE 1. Synchronous Data Timing Diagram
FIGURE 2. Hold Timing
,, ,
tCSS tCLH tCLL tDIS tPD
SCK
tCSH
tCSN
tDIN
tDH
tDF
DS500041-3
tHDS
HOLD
tHDN
tHDS
tHDN
tHZ
SO
tLZ
DS500041-6
FIGURE 3. SPI Serial Interface
MASTER MCU DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (CLK) NM25C640
SPI CHIP SELECTION
SS0 SS1 SS2 SS3
SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS
DS500041-4
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NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description
TABLE 1. Instruction Set Instruction Instruction Name Opcode
WREN WRDI RDSR WRSR READ WRITE 00000110 00000100 00000101 00000001 00000011 00000010
Operation
Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
HOLD: The HOLD pin is used in conjunction with the CS to select the device. Once the device is selected and a serial sequence is underway, HOLD may be forced low to suspend further serial communication with the device without resetting the serial sequence. Note that HOLD must be brought low while the SCK pin is low. The device must remain selected during this sequence. To resume serial communication HOLD is brought high while the SCK pin is low. The SO pin is at a high impedance state during HOLD. INVALID OP-CODE: After an invalid code is received, no data is shifted into the NM25C640, and the SO data output pin remains high impedance until a new CS falling edge reinitializes the serial communication. See Figure 5 .
MASTER: The device that generates the serial clock is designated as the master. The NM25C640 can never function as a master. SLAVE: The NM25C640 always operates as a slave as the serial clock pin is always an input. TRANSMITTER/RECEIVER: The NM25C640 has separate pins for data transmission (SO) and reception (SI). MSB: The Most Significant Bit is the first bit transmitted and received. CHIP SELECT: The chip is selected when pin CS is low. When the chip is not selected, data will not be accepted from pin SI, and the output pin SO is in high impedance. SERIAL OP-CODE: The first byte transmitted after the chip is selected with CS going low contains the op-code that defines the operation to be performed. PROTOCOL: When connected to the SPI port of a 68HC11 microcontroller, the NM25C640 accepts a clock phase of 0 and a clock polarity of 0. The SPI protocol for this device defines the byte transmitted on the SI and SO data lines for proper chip operation. See Figure 4.

FIGURE 5. Invalid Op-Code
CS SI
INVALID CODE
SO
DS500041-7
FIGURE 4. SPI Protocol
Data is clocked in on the positive SCK edge and out on the negative SCK edge.

CS SCK
...
SI
Bit 7 Bit 6
...
Bit 0
SO
Bit 7
...
Bit 1
Bit 0
DS500041-5
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NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description (Continued)
READ SEQUENCE: Reading the memory via the serial SPI link requires the following sequence. The CS line is pulled low to select the device. The READ op-code is transmitted on the SI line followed by the high order address byte (A12-A8), and the low order address byte (A7-A0). The leading three bits in the high order address byte will be ignored. After this is done, data on the SI line becomes don't care. The data (D7-D0) at the address specified is then shifted out on the SO line. If only one byte is to be read, the CS line can be pulled back to the high level. It is possible to continue the READ sequence as the byte adress is automatically incremented and data will continue to be shifted out. When the highest address is reached (1FFF), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous READ cycle. See Figure 6.
TABLE 3. Block Write Protection Levels Level Status Register Bits BP1
0 1 2 3 0 0 1 1
BP0
0 1 0 1
Array Address Protected
None 1800-1FFF 1000-1FFF 0000-1FFF
NM25C640 Rev. D.2

FIGURE 6. Read Sequence
CS SI
Read Byte H Op-Code Addr. n
Byte L Addr. n
WRITE ENABLE (WREN): When VCC is applied to the chip, it "powers up" in the write disable state. Therefore, all programming modes must be preceded by a WRITE ENABLE (WREN) instruction. Additionally, the WP must be held high during a write engble instruction. At the completion of a WRITE or WRSR cycle the device is automatically returned to the write disable state. Note that a WRITE DISABLE (WRD) instruction will also return the device to the write disable state. See Figure 8.
FIGURE 8. Write Enable
CS
SO
Data n
Data n+1
Data n+2
Data n+3
DS500041-8
SI
WREN Op-Code
READ STATUS REGISTER (RDSR) : The Read Status Register (RDSR) instruction provides access to the status register is used to interrogate the READY/BUSY and WRITE ENABLE status of the chip. Two non-volatile status register bits are used to select one of four levels of BLOCK WRITE PROTECTION. The status register format is shown in Table 2.
SO
DS500041-10
TABLE 2. Status Register Format Bit 7
X
WRITE DISABLE (WRDI): To protect against accidental data disturbance the WRITE DISABLE (WRDI) instruction disables all programming modes. See Figure 9.
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
Bit 2
Bit 1
Bit 0
FIGURE 9. Write Disable
CS
BP1
BP0
WEN
RDY
X = Don't Care.
Status register Bit 0 = 0 (RDY) indicates that the device is READY; Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0 (WEN) indicates that the device is not WRITE ENABLED; Bit 1 = 1 indicates that the device is WRITE ENABLED. Non-volatile status register Bits 2 and 3 (BP0 and BP1) indicate the level of BLOCK WRITE PROTECTION selected. The block write protection levels and corresponding status register control bits are shown in Table 3. Note that if a RDSR instruction is executed during a programming cycle only the RDY bit is valid. All other bits are 1s. See Figure 7.
SI
WRDI Op-Code
SO
DS500041-11
FIGURE 7. Read Status
CS
SI
RDSR Op-Code
SO
SR Data MSB...LSB
DS500041-9
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description (Continued)
WRITE SEQUENCE: To program the device, the WRITE PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via the WRITE ENABLE instruction and then a WRITE instruction must be executed. Moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the Block Write Protection Level. See Table 3. A WRITE command requires the following sequence. The CS line is pulled low to select the device, then the WRITE op-code is transmitted on the SI line followed by the high order address byte (A12-A8) and the low order address byte (A7-A0). The leading five bits in the high order address byte will be ignored. The address is followed by the data (D7-D0) to be written. Programming will start after the CS pin is forced back to a high level. Note that the LOW to HIGH transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 data bit. See Figure 10. At the completion of a WRITE cycle the device is automatically returned to the write disable state. If the device is not WRITE enabled, the device will ignore the WRITE instruction and return to the standby state when CS is forced high. A new CS falling edge is required to re-initialize the serial communication. WRITE STATUS REGISTER (WRSR): The WRITE STATUS REGISTER (WRSR) instruction is used to program the nonvolatile status register Bits 2 and 3 (BP0 and BP1). The WRITE PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via the WRITE ENABLE instruction and then a WRSR instruction must be executed. The WRSR command requires the following sequence. The CS line is pulled low to select the device and then the WRSR op-code is transmitted on the SI line followed by the data to be programmed. See Figure 12.

FIGURE 10. End of WRITE Sequence
CS
FIGURE 12. Write Status Register
CS
SCK
SI
WRSR Op-Code
SR Data xxxxBP1BP0xx
SI
D2
D1
D0
SO
SO
DS500041-14
DS500041-12
The READY/BUSY status of the device can be determined by executing a READ STATUS REGISTER (RDSR) instruction. Bit 0 = 1 indicates that the WRITE cycle is still in progress and Bit 0 = 0 indicates that the WRITE cycle has ended. During the WRITE programming cycle (Bit 0 = 1) only the READ STATUS REGISTER instruction is enabled. The NM25C640 is capable of a 32 byte PAGE WRITE operation. After receipt of each byte of data the five low order address bits are internally incremented by one. The eight high order bits of the address will remain constant. If the master should transmit more than 32 bytes of data, the address counter will "roll over," and the previously loaded data will be reloaded. See Figure 11.
Note that the first four bits are don't care bits followed by BP1 and BP0 then two additional don't care bits. Programming will start after the CS pin is forced back to a high level. As in the WRITE instruction the LOW to HIGH transition of the CS pin must occur during the SCK low time immediately after clocking in the last don't care bit. See Figure 13.
FIGURE 13. Start WRSR Condition
CS
SCK
FIGURE 11. 32 Byte Page Write
CS
SI
BP0
SI
Write Byte H Byte L Op-Code Addr (n) Addr (n)
Data (n)
Data (n+1)
Data (n+2)
Data (n+3)
...
Data (n+31)
SO
DS500041-15
SO
DS500041-13
The READY/BUSY status of the device can be determined by executing a READ STATUS REGISTER (RDSR) instruction. Bit 0 = 1 indicates that the WRSR cycle is still in progress and Bit 0 = 0 indicates that the WRSR cycle has ended. At the completion of a WRITE cycle the device is automatically returned to the write disable state.
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NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Small Out-Line Package (M8) Package Number M08A
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1 0.032 0.005 (0.813 0.127) RAD 0.250 - 0.005 (6.35 0.127) Pin #1 IDENT
8
7
8
+
7
6
5
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080) 0.040 Typ. (1.016)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524) 0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Package Number N08E
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NM25C640 Rev. D.2
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NM25C640 64K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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